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21143-PD
High-speed data transmission and processing capabilitie
21143-PD
High-speed data transmission and processing capabilitie
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Service & Packaging
Service & Packaging
About After Sales Service
All Parts Extended Quality Guarantee
Initiate the application within 90 days from the shipment date.
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Regarding packaging, our products are carefully packed in anti-static bags to provide ESD anti-static protection. The outer packaging is durable with secure closure. We support various packaging methods such as Tape and Reel, Cut Tape, Tube, or Tray.
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21143-PD DataSheet
Current price plan is under preparation. Please contact our customer service team for the latest pricing information. Thank you for your understanding and support!
Details
General Description The 21143 is an Ethernet LAN controller for both 100-Mb/s and 10-Mb/s data rates, which provides a direct interface to the peripheral component interconnect (PCI) local bus or the CardBus. The 21143 interfaces to the host processor by using onchip command and status registers (CSRs) and a shared host memory area, set up mainly during initialization. This minimizes processor involvement in the 21143 operation during normal reception and transmission. The 21143 is optimized for low power PCI/CardBus based systems and supports two types of power-management mechanisms. The main mechanism is based upon the OnNow architecture, which is required for PC 97 and PC 98. The alternative mechanism is based upon the older remote wake-up-LAN mechanism.Product Features ■ Fully compliant with Revision 2.1 of the PCI Local Bus Specification and with Revision 1.0 of the PCI Bus Power Management Interface Specification. ■ Fully compliant with Revision 1.0 of the Advanced Configuration and Power Interface (ACPI) Specification and with Revision 1.0 of the Network Device Class Power Management Specification, under the OnNow Architecture for Microsoft’s PC 97 Hardware Design Guide and PC 98 System Design Guide. ■ Supports IEEE 802.3 with full Auto-Negotiation algorithm of full-duplex and half-duplex operation for 10 Mb/s and 100 Mb/s (NWAY). ■ Supports IEEE 802.3 and ANSI 8802-3 Ethernet standards. ■ Supports direct memory access (DMA) and has direct interface to both the CardBus* and PCI local bus. ■ Provides glueless 32-bit PCI bus master interface. ■ Contains large independent receive and transmit FIFOs. ■ Contains internal PCS and scrambler/descrambler for MII/SYM interface for 100BASE-TX. ■ Contains onchip integrated AUI port and a 10BASE-T transceiver. ■ Supports autodetection between 10BASE-T, AUI, and MII/SYM ports. ■ Provides an upgradable boot ROM interface up to 256KB. ■ Supports remote wake-up-LAN and Magic Packet* with the SecureON™ password option. ■ Supports PCI/CardBus clock speed frequency from dc to 33 MHz; network operation with PCI clock from 20 MHz to 33 MHz. ■ Implements low-power management with two power-saving modes (sleep and snooze). ■ Implements low-power, 3.3-V CMOS technology.
Key Features
- Fully compliant with Revision 2.1 of the PCI Local Bus Specification and with Revision 1.0 of the PCI Bus Power Management Interface Specification.
- Fully compliant with Revision 1.0 of the Advanced Configuration and Power Interface (ACPI) Specification and with Revision 1.0 of the Network Device Class Power Management Specification, under the OnNow Architecture for Microsoft’s PC 97 Hardware Design Guide and PC 98 System Design Guide.
- Supports IEEE 802.3 with full Auto-Negotiation algorithm of full-duplex and half-duplex operation for 10 Mb/s and 100 Mb/s (NWAY).
- Supports IEEE 802.3 and ANSI 8802-3 Ethernet standards.
- Supports direct memory access (DMA) and has direct interface to both the CardBus and PCI local bus.
- Provides glueless 32-bit PCI bus master interface.
- Contains large independent receive and transmit FIFOs.
- Contains internal PCS and scrambler/descrambler for MII/SYM interface for 100BASE-TX.
- Contains onchip integrated AUI port and a 10BASE-T transceiver.
- Supports autodetection between 10BASE-T, AUI, and MII/SYM ports.
- Provides an upgradable boot ROM interface up to 256KB.
- Supports remote wake-up-LAN and Magic Packet with the SecureON™ password option.
- Supports PCI/CardBus clock speed frequency from dc to 33 MHz; network operation with PCI clock from 20 MHz to 33 MHz.
- Implements low-power management with two power-saving modes (sleep and snooze).
- Implements low-power, 3.3-V CMOS technology.
Specifications
The followings are basic parameters of the part selected concerning the characteristics of the part and categories it belongs to.
| Rohs Code | No | Part Life Cycle Code | Obsolete |
| Part Package Code | QFP | Pin Count ! | 144 |
| Reach Compliance Code | HTS Code ! | 8542.31.00.01 | |
| Address Bus Width ! | 32 | Boundary Scan | YES |
| Bus Compatibility | PCI; CARDBUS | Clock Frequency-Max | 33.33 MHz |
| Data Encoding/Decoding Method | BIPH-LEVEL(MANCHESTER) | Data Transfer Rate-Max | 12.5 MBps |
| External Data Bus Width | 32 | JESD-30 Code | S-PQFP-G144 |
| JESD-609 Code | e0 | Length | 28 mm |
| Low Power Mode | YES | Number of Serial I/Os | 2 |
| Number of Terminals | 144 | Operating Temperature-Max | 70 °C |
| Operating Temperature-Min | Package Body Material | PLASTIC/EPOXY | |
| Package Code | QFP | Package Equivalence Code | QFP144,1.2SQ |
| Package Shape | SQUARE | Package Style | FLATPACK |
| Power Supplies ! | 3.3,3.3/5 V | Qualification Status ! | Not Qualified |
| Seated Height-Max | 4.1 mm | Supply Current-Max | 230 mA |
| Supply Voltage-Max | 3.6 V | Supply Voltage-Min | 3 V |
| Supply Voltage-Nom | 3.3 V | Surface Mount ! | YES |
| Technology | CMOS | Temperature Grade ! | COMMERCIAL |
| Terminal Finish | TIN LEAD | Terminal Form ! | GULL WING |
| Terminal Pitch ! | 0.65 mm | Terminal Position | QUAD |
| Width | 28 mm | uPs/uCs/Peripheral ICs Type | SERIAL IO/COMMUNICATION CONTROLLER, LAN |
Datasheet PDF
Datasheets record the features, absolute maximum ratings, applications and more of the device, which benefit a lot as an overall guide to the specific application of the part.
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