AM4378BZDN100

Name: AM4378BZDN100
Rating: 4.5 (10 reviews)

Sitara processor: Arm Cortex-A9, PRU-ICSS, 3D graphics 491-NFBGA 0 to 90

6,272 Effective Inventory

AM4378BZDN100

Effective Inventory6,272

Sitara processor: Arm Cortex-A9, PRU-ICSS, 3D graphics 491-NFBGA 0 to 90

Manufacturer Part # : AM4378BZDN100
Package/Case: NFBGA-491
Brand: Texas Instruments
Product Categories : Microprocessors

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All parts procured from our supply chain network undergo a rigorous incoming inspection process. This meticulous inspection ensures that the parts received by our customers are authentic and meet the required standards. Additionally, we maintain detailed records of these inspections to ensure transparency and traceability throughout the supply chain.

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We have successfully obtained various certification standards and have established our own professional testing laboratory. This ensures that every product we supply to our customers meets the highest quality standards. We adhere to strict testing protocols to maintain the consistency and accuracy of our products. To ensure that our products are original and genuine, we also collaborate with reputable third-party testing facilities to conduct rigorous quality testing. Our commitment to quality extends to meeting industry, legal, regulatory, and ISO 9001:2015 requirements.

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Service & Packaging

About After Sales Service

All Parts Extended Quality Guarantee

Initiate the application within 90 days from the shipment date.

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Maintain the goods in their original condition as received.

Lastly, please note that the eligibility for return or exchange of goods is subject to an assessment of the actual condition of the returned items. We will evaluate the received goods before finalizing the return or exchange process. If you have any inquiries or require further assistance regarding returns or exchanges, please don't hesitate to contact us at [email protected]

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Regarding packaging, our products are carefully packed in anti-static bags to provide ESD anti-static protection. The outer packaging is durable with secure closure. We support various packaging methods such as Tape and Reel, Cut Tape, Tube, or Tray.

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AM4378BZDN100 DataSheet

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Details

What sets the AM4378BZDN100 apart is its low power consumption and industrial-grade reliability, making it a prime choice for applications in automation, control systems, and human-machine interfaces (HMI). Its ability to support various operating systems including Linux and RTOS further adds to its appeal, providing flexibility for software development. With all these features combined, it's clear that the AM4378BZDN100 is a standout microprocessor for industrial use

Key Features

Highlights
- Sitara™ARM^® Cortex^®-A9 32-Bit RISCProcessor With Processing Speed up to 1000 MHz
  - NEON™ SIMDCoprocessor and Vector Floating Point (VFPv3) Coprocessor
  - 32KB of Both L1 Instruction and Data Cache
  - 256KB of L2 Cache or L3 RAM
- 32-Bit LPDDR2, DDR3, and DDR3L Support
- General-Purpose Memory Support (NAND, NOR, SRAM) Supporting up to 16-BitECC
- SGX530 Graphics Engine
- Display Subsystem
- Programmable Real-Time Unit Subsystem and IndustrialCommunication Subsystem (PRU-ICSS)
- Real-Time Clock (RTC)
- Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With IntegratedPHY
- 10, 100, and 1000 Ethernet Switch Supporting up to TwoPorts
- Serial Interfaces:
  - Two Controller Area Network (CAN) Ports
  - Six UARTs, Two McASPs, Five McSPIs, Three I²CPorts, One QSPI, and One HDQ or 1-Wire
- Security
  - Crypto Hardware Accelerators (AES, SHA, RNG, DES, and3DES)
  - Secure Boot (Avaliable Only on AM437x High-Security[AM437xHS] Devices)
- Two 12-Bit Successive Approximation Register (SAR)ADCs
- Up to Three 32-Bit Enhanced Capture (eCAP) Modules
- Up to Three Enhanced Quadrature Encoder Pulse (eQEP) Modules
- Up to Six Enhanced High-Resolution PWM (eHRPWM) Modules
MPU Subsystem
- ARM Cortex-A9 32-Bit RISC Microprocessor With Processing Speed up to1000 MHz
- 32KB of Both L1 Instruction and Data Cache
- 256KB of L2 Cache (Option to Configure as L3 RAM)
- 256KB of On-Chip Boot ROM
- 64KB of On-Chip RAM
- Secure Control Module (SCM) (Avaliable Only on AM437xHSDevices)
- Emulation and Debug
  - JTAG
  - Embedded Trace Buffer
- Interrupt Controller
On-Chip Memory (Shared L3 RAM)
- 256KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
- Accessible to All Masters
- Supports Retention for Fast Wakeup
- Up to 512KB of Total Internal RAM(256KB of ARM Memory Configured as L3 RAM + 256KB of OCMC RAM)
External Memory Interfaces (EMIFs)
- DDR Controllers:
  - LPDDR2: 266-MHz Clock (LPDDR2-533 Data Rate)
  - DDR3 and DDR3L: 400-MHz Clock (DDR-800 Data Rate)
  - 32-Bit Data Bus
  - 2GB of Total Addressable Space
  - Supports One x32, Two x16, or Four x8 Memory DeviceConfigurations
General-Purpose Memory Controller (GPMC)
- Flexible 8- and 16-Bit Asynchronous Memory Interface With up to Seven ChipSelects (NAND, NOR, Muxed-NOR, and SRAM)
- Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
- Uses Hamming Code to Support 1-Bit ECC
Error Locator Module (ELM)
- Used With the GPMC to Locate Addresses of Data Errors From SyndromePolynomials Generated Using a BCH Algorithm
- Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCHAlgorithms
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
- Supports Protocols such asEtherCAT^®,PROFIBUS^®,PROFINET^®, and EtherNet/IP™,EnDat 2.2, and More
- Two Programmable Real-Time Units (PRUs) Subsystems With Two PRU CoresEach
  - Each Core is a 32-Bit Load and Store RISC ProcessorCapable of Running at 200 MHz
  - 12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of InstructionRAM With Single-Error Detection (Parity)
  - 8KB (PRU-ICSS1), 4KB (PRU-ICSS0) ofData RAM With Single-Error Detection (Parity)
  - Single-Cycle 32-Bit MultiplierWith 64-Bit Accumulator
  - Enhanced GPIO Module Provides Shift-In and Shift-OutSupport and Parallel Latch on External Signal
- 12KB (PRU-ICSS1 Only) of Shared RAM WithSingle-Error Detection (Parity)
- Three 120-Byte Register Banks Accessible byEach PRU
- Interrupt Controller Module (INTC) for Handling System InputEvents
- Local Interconnect Bus for Connecting Internal and External Masters tothe Resources Inside the PRU-ICSS
- Peripherals Inside the PRU-ICSS
  - One UART Port With Flow Control Pins, Supports up to 12Mbps
  - One eCAP Module
  - Two MII Ethernet Ports that SupportIndustrial Ethernet, such as EtherCAT
  - One MDIO Port
- Industrial Communication is Supported by Two PRU-ICSS Subsystems
Power, Reset, and Clock Management (PRCM) Module
- Controls the Entry and Exit of Deep-Sleep Modes
- Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-UpSequencing, and Power Domain Switch-On Sequencing
- Clocks
  - Integrated High-Frequency Oscillator Used to Generate a Reference Clock(19.2, 24, 25, and 26 MHz) for Various System and Peripheral Clocks
  - Supports Individual Clock Enable and Disable Control for Subsystems andPeripherals to Facilitate Reduced Power Consumption
  - Five ADPLLs to Generate System Clocks (MPU Subsystem,DDR Interface, USB, and Peripherals [MMC and SD, UART, SPI, I²C], L3,L4, Ethernet, GFX [SGX530], and LCD Pixel Clock)
- Power
  - Two Nonswitchable Power Domains (RTCand Wake-Up Logic [WAKE-UP])
  - Three Switchable Power Domains (MPU Subsystem, SGX530[GFX], Peripherals and Infrastructure [PER])
  - Dynamic Voltage Frequency Scaling(DVFS)
Real-Time Clock (RTC)
- Real-Time Date (Day, Month, Year, and Day of Week) and Time (Hours, Minutes,and Seconds) Information
- Internal 32.768-kHz Oscillator, RTC Logic, and 1.1-V Internal LDO
- Independent Power-On-Reset (RTC_PWRONRSTn) Input
- Dedicated Input Pin (RTC_WAKEUP) for External WakeEvents
- Programmable Alarm Can Generate Internal Interrupts to the PRCM for Wakeup orCortex-A9 for Event Notification
- Programmable Alarm Can Be Used With External Output (RTC_PMIC_EN) to Enablethe Power-Management IC to Restore Non-RTC Power Domains
Peripherals
- Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With IntegratedPHY
- Up to Two Industrial Gigabit Ethernet MACs(10, 100, and 1000 Mbps)
  - Integrated Switch
  - Each MAC Supports MII, RMII, and RGMII and MDIO Interfaces
  - Ethernet MACs and Switch Can Operate Independent of OtherFunctions
  - IEEE 1588v2 Precision Time Protocol (PTP)
- Up to Two CANPorts
  - Supports CAN Version 2 Parts A and B
- Up to Two Multichannel Audio Serial Ports(McASPs)
  - Transmit and Receive Clocks up to 50 MHz
  - Up to Four Serial Data Pins Per McASP Port With Independent TX and RXClocks
  - Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), andSimilar Formats
  - Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, andAES-3 Formats)
  - FIFO Buffers for Transmit and Receive (256 Bytes)
- Up to Six UARTs
  - All UARTs Support IrDA and CIR Modes
  - All UARTs Support RTS and CTS Flow Control
  - UART1 Supports Full Modem Control
- Up to Five Master and Slave McSPIs
  - McSPI0–McSPI2 Support up to Four ChipSelects
  - McSPI3 and McSPI4 Support up to Two Chip Selects
  - Up to 48 MHz
- One Quad-SPI
  - Supports eXecute In Place (XIP) from Serial NOR FLASH
- One Dallas 1-Wire^® and HDQ Serial Interface
- Up to Three MMC, SD, and SDIO Ports
  - 1-, 4-, and 8-Bit MMC, SD, and SDIO Modes
  - 1.8- or 3.3-V Operation on All Ports
  - Up to 48-MHz Clock
  - Supports Card Detect and Write Protect
  - Complies With MMC4.3 and SD and SDIO 2.0 Specifications
- Up to Three I²CMaster and Slave Interfaces
  - Standard Mode (up to 100 kHz)
  - Fast Mode (up to 400 kHz)
- Up to Six Banks of General-Purpose I/O (GPIO)
  - 32 GPIOs per Bank (Multiplexed With Other Functional Pins)
  - GPIOs Can be Used as Interrupt Inputs (up to Two Interrupt Inputs perBank)
- Up to Three External DMA Event Inputs That Can Also be Used as InterruptInputs
- Twelve 32-Bit General-Purpose Timers
  - DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
  - DMTIMER4–DMTIMER7 are Pinned Out
- One Public WatchdogTimer
- One Free-Running, High-Resolution 32-kHz Counter (synctimer32K)
- One Secure Watchdog Timer (Avaliable Only onAM437xHS Devices)
- SGX530 3D Graphics Engine
  - Tile-Based Architecture Delivering up to 20M Poly/sec
  - Universal Scalable Shader Engine is a Multithreaded Engine IncorporatingPixel and Vertex Shader Functionality
  - Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, andOGL2.0
  - Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and2.0
  - Fine-Grained Task Switching, Load Balancing, and PowerManagement
  - Advanced Geometry DMA-Driven Operation for Minimum CPUInteraction
  - Programmable High-Quality Image Anti-Aliasing
  - Fully Virtualized Memory Addressing for OS Operation in a Unified MemoryArchitecture
- Display Subsystem
  - Display Modes
    - Programmable Pixel Memory Formats (Palletized: 1-, 2-, 4-, and 8-Bits Per Pixel; RGB 16- and 24-Bits Per Pixel; and YUV 4:2:2)
    - 256- × 24-Bit Entries Palette in RGB
    - Up to 2048 × 2048 Resolution
  - Display Support
    - Four Types of Displays Are Supported: Passive and Active Colors; Passive and Active Monochromes
    - 4- and 8-Bit Monochrome Passive Panel Interface Support (15 Grayscale Levels Supported Using Dithering Block)
    - RGB 8-Bit Color Passive Panel Interface Support (3,375 Colors Supported for Color Panel Using Dithering Block)
    - RGB 12-, 16-, 18-, and 24-Bit Active Panel Interface Support (Replicated or Dithered Encoded Pixel Values)
    - Remote Frame Buffer (Embedded in the LCD Panel) Support Through the RFBI Module
    - Partial Refresh of the Remote Frame Buffer Through the RFBI Module
    - Partial Display
    - Multiple Cycles Output Format on 8-, 9-, 12-, and 16-Bit Interface (TDM)
  - Signal Processing
    - Overlay and Windowing Support for One Graphics Layer (RGB or CLUT) and Two Video Layers (YUV 4:2:2, RGB16, and RGB24)
    - RGB 24-Bit Support on the Display Interface, Optionally Dithered to RGB 18‑Bit Pixel Output Plus 6-Bit Frame Rate Control (Spatial and Temporal)
    - Transparency Color Key (Source and Destination)
    - Synchronized Buffer Update
    - Gamma Curve Support
    - Multiple-Buffer Support
    - Cropping Support
    - Color Phase Rotation
- Two 12-Bit SAR ADCs (ADC0,ADC1)
  - 867K Samples Per Second
  - Input Can Be Selected from Any of the Eight Analog Inputs MultiplexedThrough an 8:1 Analog Switch
  - ADC0 Can Be Configured to Operate as a 4‑, 5-, or 8-Wire Resistive TouchScreen Controller (TSC)
- Up to Three 32-Bit eCAP Modules
  - Configurable as Three Capture Inputs or Three Auxiliary PWMOutputs
- Up to Six Enhanced eHRPWM Modules
  - Dedicated 16-Bit Time-Base Counter With Time and FrequencyControls
  - Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or ThreeDual-Edge Asymmetric Outputs
- Up to Three 32-Bit eQEP Modules
Device Identification
- Factory Programmable Electrical Fuse Farm (FuseFarm)
  - Production ID
  - Device Part Number (Unique JTAG ID)
  - Device Revision (Readable by Host ARM)
  - Security Keys (Avaliable Only on AM437xHS Devices)
  - Feature Identification
Debug Interface Support
- JTAG and cJTAG for ARM (Cortex-A9 and PRCM) and PRU-ICSSDebug
- Supports Real-Time Trace Pins (for Cortex-A9)
- 64-KB Embedded Trace Buffer (ETB)
- Supports Device Boundary Scan
- Supports IEEE 1500
DMA
- On-Chip Enhanced DMA Controller (EDMA) Has Three Third-Party TransferControllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64Programmable Logical Channels and Eight QDMA Channels
- EDMA is Used for:
  - Transfers to and from On-Chip Memories
  - Transfers to and from External Storage (EMIF, GPMC, and SlavePeripherals)
InterProcessor Communication (IPC)
- Integrates Hardware-Based Mailbox for IPC and Spinlock for ProcessSynchronization Between the Cortex-A9, PRCM, and PRU-ICSS
Boot Modes
- Boot Mode is Selected Through Boot Configuration Pins Latched on the RisingEdge of the PWRONRSTn Reset Input Pin
Camera
- Dual Port 8- and 10-Bit BT656 Interface
- Dual Port 8- and 10-Bit Including External Syncs
- Single Port 12-Bit
- YUV422/RGB422 and BT656 Input Format
- RAW Format
- Pixel Clock Rate up to 75 MHz
Package
- 491-Pin BGA Package (17-mm × 17-mm) (ZDN Suffix), 0.65-mm Ball Pitch With ViaChannel Array Technology to Enable Low-Cost Routing

Specifications

The followings are basic parameters of the part selected concerning the characteristics of the part and categories it belongs to.

Rohs Code	Yes	Part Life Cycle Code	Active
Part Package Code	BGA	Pin Count !	491
Reach Compliance Code	compliant	ECCN Code	5A992.C
HTS Code !	8542.31.00.01	JESD-30 Code	S-PBGA-B491
JESD-609 Code	e1	Length	17 mm
Moisture Sensitivity Level	3	Number of Terminals	491
Operating Temperature-Max	90 °C	Operating Temperature-Min
Package Body Material	PLASTIC/EPOXY	Package Code	LFBGA
Package Equivalence Code	BGA491,25X25,25	Package Shape	SQUARE
Package Style	GRID ARRAY, LOW PROFILE, FINE PITCH	Peak Reflow Temperature (Cel)	260
Seated Height-Max	1.3 mm	Supply Voltage-Max	1.378 V
Supply Voltage-Min	1.272 V	Supply Voltage-Nom	1.325 V
Surface Mount !	YES	Technology	CMOS
Temperature Grade !	OTHER	Terminal Finish	TIN SILVER COPPER
Terminal Form !	BALL	Terminal Pitch !	0.65 mm
Terminal Position	BOTTOM	Time@Peak Reflow Temperature-Max (s)	30
Width	17 mm	uPs/uCs/Peripheral ICs Type	SYSTEM ON CHIP

Datasheet PDF

Datasheets record the features, absolute maximum ratings, applications and more of the device, which benefit a lot as an overall guide to the specific application of the part.

Preliminary Specification AM4378BZDN100 PDF Download

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