Basic Knowledge of Phase-Locked Loop (PLL) Design and Simulation

Phase-Locked Loop (PLL) is a frequency and phase synchronization technique commonly used in the field of communications. It utilizes feedback control principles to synchronize the clock output of a circuit with an external reference clock. When there are changes in the frequency or phase of the reference clock, the PLL detects these variations and adjusts the output frequency through its internal feedback system until both clocks are synchronized, resulting in a stable frequency signal.

Principle of PLL Design: A PLL is a phase-tracking system. The basic circuit diagram of a PLL is as follows:

It mainly consists of a phase detector (PD), a loop filter (LF), and a voltage-controlled oscillator (VCO). When used as a frequency synthesizer, a digital divider should be inserted between the output and input signals. The phase detector compares the phase of the output signal with the reference signal.

The loop filter removes high-frequency components and noise from the error voltage to meet the performance requirements of the loop and improve system stability. The voltage-controlled oscillator is controlled by a control voltage, which adjusts its frequency to approach the frequency of the reference signal. As a result, the frequency difference between the two signals decreases until it is eliminated and locked.

In summary, the working principle of a PLL can be described as follows. The phase detector compares the phase of the input signal with the reference signal and generates an error voltage reflecting the phase difference between the two signals. This error voltage is filtered by the loop filter to obtain a control voltage. The VCO's frequency is adjusted to approach the frequency of the reference signal until both frequencies are equal and phase-locked. The phase difference between the two signals after locking is a fixed and stable value.

Therefore, by utilizing the phase-tracking function of the PLL, it is possible to achieve synchronization between the output signal and the reference signal, with minimal steady-state phase difference and no frequency difference.

To establish the mathematical model of a PLL, it is necessary to first establish mathematical models for the phase detector, loop filter, and voltage-controlled oscillator.

Phase Detector

The phase detector (PD), also known as a phase comparator, is used to compare the phase difference between two output signals.

There are different types of phase detectors based on their characteristics, including sinusoidal, triangular, and sawtooth waveforms. For analysis purposes, sinusoidal phase detectors are commonly used, and a typical sinusoidal phase detector can be constructed by cascading an analog multiplier and a low-pass filter.

Loop Filter

The loop filter (LF) is a linear low-pass filter used to remove high-frequency components and noise from the error voltage. It plays a crucial role in determining the loop parameters. The loop filter consists of linear components such as resistors, capacitors, and operational amplifiers, making it a linear system.

The commonly used loop filters include RC integral filters, passive proportional-integral (PI) filters, and active integral filters. The active proportional-integral (PI) filter is composed of operational amplifiers.

Voltage-Controlled Oscillator

The voltage-controlled oscillator (VCO) is a voltage-to-frequency converter that acts as a controlled oscillator in the loop. Its oscillation frequency should vary linearly with the input control voltage. The VCO performs an integral function in the phase-locked loop and is also referred to as the inherent integral element in the loop.

Loop Phase Model and Basic Equations

By combining the models of the phase detector, loop filter, and voltage-controlled oscillator, we obtain the model of the phase-locked loop.

In practical applications, phase-locked loops often appear in the form of frequency synthesizers. The main difference between a frequency synthesizer and the basic phase-locked loop circuit is the inclusion of a digital divider in the feedback loop. For ease of explanation, the frequency synthesizer is commonly referred to as a phase-locked loop circuit.

Performance Parameters of Phase-Locked Loops:

Frequency Accuracy: The difference between the actual output frequency and the nominal output frequency, typically determined by the division ratio N and the reference source fref.

Frequency Stability: The relative change in frequency (f - f0) / f0 within a certain time interval, usually measured in ppm (parts per million) or ppb (parts per billion). This parameter is generally determined by the reference source fref.

Minimum Interval between Adjacent Output Frequencies: For integer division, the frequency accuracy is equal to fref; for fractional division, the frequency accuracy can be arbitrarily small.

Frequency Range: The range of output frequencies of the phase-locked loop system, determined by the VCO frequency range and the divider inside the phase-locked loop chip.

Settling Time: The time it takes for the phase-locked loop system's output signal to transition from one frequency to another and settle into a stable state. This parameter is determined by the system damping factor and loop bandwidth.

Spectral Purity: This parameter is measured by the phase noise and spurious components of the output signal. In-band phase noise is mainly determined by the reference source, phase detector, and charge pump, while out-of-band phase noise is mainly determined by the VCO.

Design and Simulation Objectives for Phase-Locked Loop (PLL) Circuit using ADS

The objective is to use the integrated PLL design tool in ADS to generate the overall circuit of the desired PLL design and simulate its performance parameters.

Specifications:

• VCO Output Frequency: 900MHz ± 10MHz.
• VCO Control Voltage Gain: 12MHz/V.
• VCO Phase Noise: Less than -100dBc/Hz at 100kHz offset.
• Reference Source Frequency: 10MHz.
• System Frequency Spacing: 200kHz.
• Loop Filter Loop Bandwidth: Wc = 10kHz.
• Phase Margin: 45 degrees to 50 degrees.
• Locking Time: Less than 200us.

PLL Loop Filter Design

The loop filter determines the spectral purity, locking time, and system stability of the PLL circuit.

Please note that the remaining steps for PLL circuit design and simulation, including the phase detector, VCO, and overall system analysis, require more detailed specifications and design considerations.