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JS28F256P30BF
Flash, 16MX16, 110ns, PDSO56, LEAD FREE, TSOP-56JS28F256P30BF
Flash, 16MX16, 110ns, PDSO56, LEAD FREE, TSOP-56
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JS28F256P30BF DataSheet
Current price plan is under preparation. Please contact our customer service team for the latest pricing information. Thank you for your understanding and support!
Details
IntroductionThis document provides information about the Intel StrataFlash® Embedded Memory (P30) device and describes its features, operation, and specifications.Product Features■ High performance — 85/88 ns initial access — 40 MHz with zero wait states, 20 ns clock-to data output synchronous-burst read mode — 25 ns asynchronous-page read mode — 4-, 8-, 16-, and continuous-word burst mode — Buffered Enhanced Factory Programming (BEFP) at 5 µs/byte (Typ) — 1.8 V buffered programming at 7 µs/byte (Typ)■ Architecture — Multi-Level Cell Technology: Highest Density at Lowest Cost — Asymmetrically-blocked architecture — Four 32-KByte parameter blocks: top or bottom configuration — 128-KByte main blocks■ Voltage and Power —VCC(core) voltage: 1.7 V – 2.0 V —VCCQ (I/O) voltage: 1.7 V – 3.6 V — Standby current: 55 µA (Typ) for 256-Mbit — 4-Word synchronous read current: 13 mA (Typ) at 40 MHz■ Quality and Reliability — Operating temperature: –40 °C to +85 °C • 1-Gbit in SCSP is –30 °C to +85 °C — Minimum 100,000 erase cycles per block — ETOX™ VIII process technology (130 nm)■ Security — One-Time Programmable Registers: • 64 unique factory device identifier bits • 64 user-programmable OTP bits • Additional 2048 user-programmable OTP bits — Selectable OTP Space in Main Array: • 4x32KB parameter blocks + 3x128KB main blocks (top or bottom configuration) — Absolute write protection: VPP= VSS — Power-transition erase/program lockout — Individual zero-latency block locking — Individual block lock-down■ Software — 20 µs (Typ) program suspend — 20 µs (Typ) erase suspend —Intel® Flash Data Integrator optimized — Basic Command Set and Extended Command Set compatible — Common Flash Interface capable■ Density and Packaging — 64/128/256-Mbit densities in 56-Lead TSOP package — 64/128/256/512-Mbit densities in 64-Ball Intel®Easy BGA package — 64/128/256/512-Mbit and 1-Gbit densities in Intel®QUAD+ SCSP — 16-bit wide data bus
Key Features
- High performance
- — 85/88 ns initial access
- — 40 MHz with zero wait states, 20 ns clock-to data output synchronous-burst read mode
- — 25 ns asynchronous-page read mode
- — 4-, 8-, 16-, and continuous-word burst mode
- — Buffered Enhanced Factory Programming (BEFP) at 5 µs/byte (Typ)
- — 1.8 V buffered programming at 7 µs/byte (Typ)
- Architecture
- — Multi-Level Cell Technology: Highest Density at Lowest Cost
- — Asymmetrically-blocked architecture
- — Four 32-KByte parameter blocks: top or bottom configuration
- — 128-KByte main blocks
- Voltage and Power
- —VCC(core) voltage: 1.7 V – 2.0 V
- —VCCQ (I/O) voltage: 1.7 V – 3.6 V
- — Standby current: 55 µA (Typ) for 256-Mbit
- — 4-Word synchronous read current: 13 mA (Typ) at 40 MHz
- Quality and Reliability
- — Operating temperature: –40 °C to +85 °C
- 1-Gbit in SCSP is –30 °C to +85 °C
- — Minimum 100,000 erase cycles per block
- — ETOX™ VIII process technology (130 nm)
- Security
- — One-Time Programmable Registers:
- 64 unique factory device identifier bits
- 64 user-programmable OTP bits
- Additional 2048 user-programmable OTP bits
- — Selectable OTP Space in Main Array:
- 4x32KB parameter blocks + 3x128KB main blocks (top or bottom configuration)
- — Absolute write protection: VPP= VSS
- — Power-transition erase/program lockout
- — Individual zero-latency block locking
- — Individual block lock-down
- Software
- — 20 µs (Typ) program suspend
- — 20 µs (Typ) erase suspend
- —Intel® Flash Data Integrator optimized
- — Basic Command Set and Extended Command Set compatible
- — Common Flash Interface capable
- Density and Packaging
- — 64/128/256-Mbit densities in 56-Lead TSOP package
- — 64/128/256/512-Mbit densities in 64-Ball Intel®Easy BGA package
- — 64/128/256/512-Mbit and 1-Gbit densities in Intel®QUAD+ SCSP
- — 16-bit wide data bus
Specifications
The followings are basic parameters of the part selected concerning the characteristics of the part and categories it belongs to.
| Pbfree Code | Yes | Rohs Code | Yes |
| Part Life Cycle Code | Active | Part Package Code | TSOP |
| Pin Count ! | 56 | Reach Compliance Code | compliant |
| ECCN Code | EAR99 | HTS Code ! | 8542.32.00.51 |
| Access Time-Max | 110 ns | Additional Feature ! | ASYNCHRONOUS READ MODE |
| Boot Block | BOTTOM | Clock Frequency-Max (fCLK) | 40 MHz |
| Command User Interface | YES | Common Flash Interface | YES |
| Data Polling | NO | JESD-30 Code | R-PDSO-G56 |
| JESD-609 Code | e3 | Length | 18.4 mm |
| Memory Density | 268435456 bit | Memory IC Type | FLASH |
| Memory Width | 16 | Number of Functions | 1 |
| Number of Sectors/Size | 4,255 | Number of Terminals | 56 |
| Number of Words | 16777216 words | Number of Words Code | 16000000 |
| Operating Mode ! | SYNCHRONOUS | Operating Temperature-Max | 85 °C |
| Operating Temperature-Min | -40 °C | Organization | 16MX16 |
| Package Body Material | PLASTIC/EPOXY | Package Code | TSSOP |
| Package Equivalence Code | TSSOP56,.8,20 | Package Shape | RECTANGULAR |
| Package Style | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH | Parallel/Serial | PARALLEL |
| Power Supplies ! | 1.8,1.8/3.3 V | Programming Voltage ! | 1.8 V |
| Qualification Status ! | Not Qualified | Seated Height-Max | 1.2 mm |
| Sector Size | 16K,64K | Standby Current-Max | 0.00021 A |
| Supply Current-Max | 0.031 mA | Supply Voltage-Max (Vsup) | 2 V |
| Supply Voltage-Min (Vsup) | 1.7 V | Supply Voltage-Nom (Vsup) | 1.8 V |
| Surface Mount ! | YES | Technology | CMOS |
| Temperature Grade ! | INDUSTRIAL | Terminal Finish | MATTE TIN |
| Terminal Form ! | GULL WING | Terminal Pitch ! | 0.5 mm |
| Terminal Position | DUAL | Toggle Bit | NO |
| Type | NOR TYPE | Width | 14 mm |
Datasheet PDF
Datasheets record the features, absolute maximum ratings, applications and more of the device, which benefit a lot as an overall guide to the specific application of the part.
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