H5DU5182ETR-E3C
DDR DRAM, 64MX8, 0.7ns, CMOS, PBGA60, ROHS COMPLIANT, FBGA-60H5DU5182ETR-E3C
DDR DRAM, 64MX8, 0.7ns, CMOS, PBGA60, ROHS COMPLIANT, FBGA-60
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Quality Assurance
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Certification
We have successfully obtained various certification standards and have established our own professional testing laboratory. This ensures that every product we supply to our customers meets the highest quality standards. We adhere to strict testing protocols to maintain the consistency and accuracy of our products. To ensure that our products are original and genuine, we also collaborate with reputable third-party testing facilities to conduct rigorous quality testing. Our commitment to quality extends to meeting industry, legal, regulatory, and ISO 9001:2015 requirements.
Shipping & Payment
Shipping & Payment
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Service & Packaging
Service & Packaging
About After Sales Service
All Parts Extended Quality Guarantee
Initiate the application within 90 days from the shipment date.
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H5DU5182ETR-E3C DataSheet
Current price plan is under preparation. Please contact our customer service team for the latest pricing information. Thank you for your understanding and support!
Details
The H5DU2562GFR is a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.FEATURES •VDD, VDDQ= 2.5V +/- 0.2V • All inputs and outputs are compatible with SSTL_2 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous - data transaction aligned to bidirectional data strobe (DQS) • x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O • Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) • On chip DLL align DQ and DQS transition with CK transition • DM mask write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 2/2.5 (DDR200, 266, 333), 3 (DDR400) and 4 (DDR500) supported • Programmable burst length 2/4/8 with both sequential and interleave mode • Internal four bank operations with single pulsed/RAS • Auto refresh and self refresh supported • tRAS lock out function supported • 8192 refresh cycles/64ms •60 Ball FBGA Package Type • This product is in compliance with the directive pertaining of RoHS.
Key Features
- VDD, VDDQ= 2.5V +/- 0.2V
- All inputs and outputs are compatible with SSTL_2 interface
- Fully differential clock inputs (CK, /CK) operation
- Double data rate interface
- Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
- x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O
- Data outputs on DQS edges when read (edged DQ)
- Data inputs on DQS centers when write (centered DQ)
- On chip DLL align DQ and DQS transition with CK transition
- DM mask write data-in at the both rising and falling edges of the data strobe
- All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
- Programmable CAS latency 2/2.5 (DDR200, 266, 333), 3 (DDR400) and 4 (DDR500) supported
- Programmable burst length 2/4/8 with both sequential and interleave mode
- Internal four bank operations with single pulsed/RAS
- Auto refresh and self refresh supported
- tRAS lock out function supported
- 8192 refresh cycles/64ms
- 60 Ball FBGA Package Type
- This product is in compliance with the directive pertaining of RoHS.
Specifications
The followings are basic parameters of the part selected concerning the characteristics of the part and categories it belongs to.
Rohs Code | Yes | Part Life Cycle Code | Obsolete |
Part Package Code | BGA | Pin Count ! | 60 |
Reach Compliance Code | ECCN Code | EAR99 | |
HTS Code ! | 8542.32.00.28 | Access Mode ! | FOUR BANK PAGE BURST |
Access Time-Max | 0.7 ns | Additional Feature ! | AUTO/SELF REFRESH |
Clock Frequency-Max (fCLK) | 200 MHz | I/O Type | COMMON |
Interleaved Burst Length | 2,4,8 | JESD-30 Code | R-PBGA-B60 |
JESD-609 Code | e6 | Length | 12 mm |
Memory Density | 536870912 bit | Memory IC Type | DDR1 DRAM |
Memory Width | 8 | Number of Functions | 1 |
Number of Ports ! | 1 | Number of Terminals | 60 |
Number of Words | 67108864 words | Number of Words Code | 64000000 |
Operating Mode ! | SYNCHRONOUS | Operating Temperature-Max | 70 °C |
Operating Temperature-Min | Organization | 64MX8 | |
Output Characteristics | 3-STATE | Package Body Material | PLASTIC/EPOXY |
Package Code | VBGA | Package Equivalence Code | TSSOP66,.46 |
Package Shape | RECTANGULAR | Package Style | GRID ARRAY, VERY THIN PROFILE |
Peak Reflow Temperature (Cel) | 260 | Power Supplies ! | 2.5 V |
Qualification Status ! | Not Qualified | Refresh Cycles | 8192 |
Seated Height-Max | 1 mm | Self Refresh | YES |
Sequential Burst Length | 2,4,8 | Standby Current-Max | 0.005 A |
Supply Current-Max | 0.26 mA | Supply Voltage-Max (Vsup) | 2.7 V |
Supply Voltage-Min (Vsup) | 2.3 V | Supply Voltage-Nom (Vsup) | 2.5 V |
Surface Mount ! | YES | Technology | CMOS |
Temperature Grade ! | COMMERCIAL | Terminal Finish | Tin/Bismuth (Sn98Bi2) |
Terminal Form ! | BALL | Terminal Pitch ! | 1 mm |
Terminal Position | BOTTOM | Time@Peak Reflow Temperature-Max (s) | 20 |
Width | 8 mm |
Datasheet PDF
Datasheets record the features, absolute maximum ratings, applications and more of the device, which benefit a lot as an overall guide to the specific application of the part.
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